mirror of
https://github.com/stargieg/bacnet-stack
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65 lines
2.4 KiB
C
65 lines
2.4 KiB
C
/**************************************************************************
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*
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* Copyright (C) 2009 Steve Karg <skarg@users.sourceforge.net>
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*********************************************************************/
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#include "hardware.h"
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/* me */
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#include "init.h"
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void init(
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void)
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{
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/* clear the MCU Status Register */
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MCUSR = 0;
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/* Initialize the Clock Prescaler */
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/* The default CLKPSx bits are factory set to 0011 */
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/* Enable the Clock Prescaler */
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CLKPR = _BV(CLKPCE);
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/* CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor
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------ ------ ------ ------ ---------------------
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0 0 0 0 1
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0 0 0 1 2
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0 0 1 0 4
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0 0 1 1 8
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0 1 0 0 16
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0 1 0 1 32
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0 1 1 0 64
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0 1 1 1 128
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1 0 0 0 256
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1 x x x Reserved
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*/
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/* Set the CLKPS3..0 bits to Prescaler of 1 */
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CLKPR = 0;
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/* Initialize I/O ports */
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/* For Port DDRx (Data Direction) Input=0, Output=1 */
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/* For Port PORTx (Bit Value) TriState=0, High=1 */
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DDRA = 0;
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PORTA = 0;
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DDRB = 0;
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PORTB = 0;
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DDRC = 0;
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PORTC = 0;
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DDRD = 0;
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PORTD = 0;
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}
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