mirror of
https://github.com/stargieg/bacnet-stack
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101 lines
3.7 KiB
C
101 lines
3.7 KiB
C
/**************************************************************************
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*
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* Copyright (C) 2007 Steve Karg <skarg@users.sourceforge.net>
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*********************************************************************/
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#ifndef HARDWARE_H
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#define HARDWARE_H
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#include <p18f6720.h>
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#include <stdint.h>
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#include <stdbool.h>
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#define RS485_TX_ENABLE PORTEbits.RE3
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#define RS485_RX_DISABLE PORTGbits.RG0
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#define TURN_OFF_COMPARATORS() CMCON = 0x07
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enum INT_STATE { INT_DISABLED, INT_ENABLED, INT_RESTORE };
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#define RESTART_WDT() { _asm CLRWDT _endasm }
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/* *************************************************************************
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define ENABLE_GLOBAL_INT() INTCONbits.GIE = 1 £
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#define DISABLE_GLOBAL_INT() INTCONbits.GIE = 0 £
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#define ENABLE_PERIPHERAL_INT() INTCONbits.PEIE = 1 £
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#define DISABLE_PERIPHERAL_INT() INTCONbits.PEIE = 0
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*************************************************************************** */
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#define ENABLE_HIGH_INT() INTCONbits.GIE = 1
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#define DISABLE_HIGH_INT() INTCONbits.GIE = 0
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#define ENABLE_LOW_INT() INTCONbits.PEIE = 1
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#define DISABLE_LOW_INT() INTCONbits.PEIE = 0
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#define ENABLE_TIMER0_INT() INTCONbits.TMR0IE = 1
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#define DISABLE_TIMER0_INT() INTCONbits.TMR0IE = 0
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#define ENABLE_TIMER2_INT() PIE1bits.TMR2IE = 1
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#define DISABLE_TIMER2_INT() PIE1bits.TMR2IE = 0
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#define ENABLE_TIMER4_INT() PIE3bits.TMR4IE = 1
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#define DISABLE_TIMER4_INT() PIE3bits.TMR4IE = 0
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#define ENABLE_CCP2_INT() PIE2bits.CCP2IE = 1
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#define DISABLE_CCP2_INT() PIE2bits.CCP2IE = 0
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#define ENABLE_CCP1_INT() PIE1bits.CCP1IE = 1
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#define DISABLE_CCP1_INT() PIE1bits.CCP1IE = 0
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#define ENABLE_ABUS_INT() PIE1bits.SSPIE = 1
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#define DISABLE_ABUS_INT() PIE1bits.SSPIE = 0
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#define CLEAR_ABUS_FLAG() PIR1bits.SSPIF = 0
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#define SETUP_CCP1(x) CCP1CON = x
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#define SETUP_CCP2(x) CCP2CON = x
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#define DISABLE_RX_INT() PIE1bits.RCIE = 0
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#define ENABLE_RX_INT() PIE1bits.RCIE = 1
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#define DISABLE_TX_INT() PIE1bits.TXIE = 0
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#define ENABLE_TX_INT() PIE1bits.TXIE = 1
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#if CLOCKSPEED == 20
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#define DELAY_US(x) { _asm \
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MOVLW x \
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LOOP: \
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NOP \
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NOP \
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DECFSZ WREG, 1, 0 \
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BRA LOOP \
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_endasm }
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#endif
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#define setup_timer4(mode, period, postscale) \
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T4CON = (mode | (postscale - 1) << 3); \
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PR4 = period
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#define setup_timer2(mode, period, postscale) \
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T2CON = (mode | (postscale - 1) << 3); \
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PR2 = period
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#endif /* HARDWARE_H */
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