mirror of
https://github.com/stargieg/bacnet-stack
synced 2025-10-26 23:35:52 +08:00
370 lines
15 KiB
C
370 lines
15 KiB
C
/* ***************************************************************************** */
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/* */
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/* Purpose: Set up the 16-bit Timer/Counter */
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/* */
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/* We will use Timer Channel 0 to develop a 1 msec interrupt. */
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/* */
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/* The AT91SAM7S-EK board has a 18,432,000 hz crystal oscillator. */
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/* */
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/* MAINCK = 18432000 hz */
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/* PLLCK = (MAINCK / DIV) * (MUL + 1) = 18432000/14 * (72 + 1) */
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/* PLLCLK = 1316571 * 73 = 96109683 hz */
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/* */
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/* MCK = PLLCLK / 2 = 96109683 / 2 = 48054841 hz */
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/* */
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/* TIMER_CLOCK5 = MCK / 1024 = 48054841 / 1024 = 46928 hz */
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/* */
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/* TIMER_CLOCK5 Period = 1 / 46928 = 21.309239686 microseconds */
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/* */
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/* A little algebra: .001 sec = count * 21.3092396896*10**-6 */
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/* count = .001 / 21.3092396896*10**-6 */
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/* count = 46.928 */
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/* */
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/* */
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/* Therefore: set Timer Channel 0 register RC to 46*milliseconds */
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/* turn on capture mode WAVE = 0 */
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/* enable the clock CLKEN = 1 */
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/* select TIMER_CLOCK5 TCCLKS = 100 */
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/* clock is NOT inverted CLKI = 0 */
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/* enable RC compare CPCTRG = 1 */
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/* enable RC compare interrupt CPCS = 1 */
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/* disable all the other timer 0 interrupts */
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/* */
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/* Author: James P Lynch May 12, 2007 */
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/* Modified by Steve Karg */
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/* Changed timer to 1ms. */
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/* Encapsulated the intialization */
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/* ***************************************************************************** */
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/**********************************************************
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Header files
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**********************************************************/
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#include <stdint.h>
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#include "board.h"
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#include "dlmstp.h"
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/* global variable counts interrupts */
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volatile unsigned long Timer_Milliseconds;
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/* MS/TP Silence Timer */
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static volatile int SilenceTime;
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static void Timer0_Setup(
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int milliseconds)
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{
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/* TC Block Control Register TC_BCR (read/write) */
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/* */
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/* |------------------------------------------------------------------|------| */
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/* | SYNC | */
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/* |------------------------------------------------------------------|------| */
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/* 31 1 0 */
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/* */
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/* SYNC = 0 (no effect) <===== take default */
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/* SYNC = 1 (generate software trigger for all 3 timer channels simultaneously) */
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/* */
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/* create a pointer to TC Global Register structure */
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AT91PS_TCB pTCB = AT91C_BASE_TCB;
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/* SYNC trigger not used */
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pTCB->TCB_BCR = 0;
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/* TC Block Mode Register TC_BMR (read/write) */
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/* */
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/* |-------------------------------------|-----------|-----------|-----------| */
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/* | TC2XC2S TCXC1S TC0XC0S | */
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/* |-------------------------------------|-----------|-----------|-----------| */
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/* 31 5 4 3 2 1 0 */
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/* */
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/* TC0XC0S Select = 00 TCLK0 (PA4) */
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/* = 01 none <===== we select this one */
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/* = 10 TIOA1 (PA15) */
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/* = 11 TIOA2 (PA26) */
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/* */
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/* TCXC1S Select = 00 TCLK1 (PA28) */
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/* = 01 none <===== we select this one */
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/* = 10 TIOA0 (PA15) */
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/* = 11 TIOA2 (PA26) */
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/* */
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/* TC2XC2S Select = 00 TCLK2 (PA29) */
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/* = 01 none <===== we select this one */
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/* = 10 TIOA0 (PA00) */
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/* = 11 TIOA1 (PA26) */
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/* */
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/* external clocks not used */
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pTCB->TCB_BMR = 0x15;
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/* TC Channel Control Register TC_CCR (read/write) */
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/* */
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/* |----------------------------------|--------------|------------|-----------| */
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/* | SWTRG CLKDIS CLKENS | */
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/* |----------------------------------|--------------|------------|-----------| */
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/* 31 2 1 0 */
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/* */
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/* CLKEN = 0 no effect */
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/* CLKEN = 1 enables the clock <===== we select this one */
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/* */
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/* CLKDIS = 0 no effect <===== take default */
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/* CLKDIS = 1 disables the clock */
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/* */
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/* SWTRG = 0 no effect */
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/* SWTRG = 1 software trigger aserted counter reset and clock starts <===== we select this one */
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/* */
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/* create a pointer to channel 0 Register structure */
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AT91PS_TC pTC = AT91C_BASE_TC0;
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/* enable the clock and start it */
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pTC->TC_CCR = 0x5;
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/* TC Channel Mode Register TC_CMR (read/write) */
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/* */
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/* |-----------------------------------|------------|---------------| */
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/* | LDRB LDRA | */
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/* |-----------------------------------|------------|---------------| */
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/* 31 19 18 17 16 */
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/* */
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/* |----------|---------|--------------|------------|---------------| */
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/* |WAVE = 0 CPCTRG ABETRG ETRGEDG | */
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/* |----------|---------|--------------|------------|---------------| */
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/* 15 14 13 11 10 9 8 */
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/* */
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/* |----------|---------|--------------|------------|---------------| */
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/* | LDBDIS LDBSTOP BURST CLKI TCCLKS | */
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/* |----------|---------|--------------|------------|---------------| */
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/* 7 6 5 4 3 2 0 */
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/* */
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/* CLOCK SELECTION */
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/* TCCLKS = 000 TIMER_CLOCK1 (MCK/2 = 24027420 hz) */
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/* 001 TIMER_CLOCK2 (MCK/8 = 6006855 hz) */
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/* 010 TIMER_CLOCK3 (MCK/32 = 1501713 hz) */
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/* 011 TIMER_CLOCK4 (MCK/128 = 375428 hz) */
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/* 100 TIMER_CLOCK5 (MCK/1024 = 46928 hz) <===== we select this one */
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/* 101 XC0 */
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/* 101 XC1 */
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/* 101 XC2 */
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/* */
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/* CLOCK INVERT */
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/* CLKI = 0 counter incremented on rising clock edge <===== we select this one */
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/* CLKI = 1 counter incremented on falling clock edge */
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/* */
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/* BURST SIGNAL SELECTION */
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/* BURST = 00 clock is not gated by any external system <===== take default */
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/* 01 XC0 is anded with the clock */
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/* 10 XC1 is anded with the clock */
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/* 11 XC2 is anded with the clock */
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/* */
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/* COUNTER CLOCK STOPPED WITH RB LOADING */
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/* LDBSTOP = 0 counter clock is not stopped when RB loading occurs <===== take default */
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/* = 1 counter clock is stopped when RB loading occur */
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/* */
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/* COUNTER CLOCK DISABLE WITH RB LOADING */
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/* LDBDIS = 0 counter clock is not disabled when RB loading occurs <===== take default */
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/* = 1 counter clock is disabled when RB loading occurs */
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/* */
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/* EXTERNAL TRIGGER EDGE SELECTION */
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/* ETRGEDG = 00 (none) <===== take default */
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/* 01 (rising edge) */
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/* 10 (falling edge) */
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/* 11 (each edge) */
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/* */
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/* TIOA OR TIOB EXTERNAL TRIGGER SELECTION */
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/* ABETRG = 0 (TIOA is used) <===== take default */
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/* 1 (TIOB is used) */
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/* */
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/* RC COMPARE TRIGGER ENABLE */
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/* CPCTRG = 0 (RC Compare has no effect on the counter and its clock) */
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/* 1 (RC Compare resets the counter and starts the clock) <===== we select this one */
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/* */
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/* WAVE */
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/* WAVE = 0 Capture Mode is enabled <===== we select this one */
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/* 1 Waveform Mode is enabled */
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/* */
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/* RA LOADING SELECTION */
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/* LDRA = 00 none) <===== take default */
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/* 01 (rising edge of TIOA) */
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/* 10 (falling edge of TIOA) */
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/* 11 (each edge of TIOA) */
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/* */
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/* RB LOADING SELECTION */
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/* LDRB = 00 (none) <===== take default */
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/* 01 (rising edge of TIOA) */
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/* 10 (falling edge of TIOA) */
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/* 11 (each edge of TIOA) */
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/* */
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/* TCCLKS = 1 (TIMER_CLOCK5) */
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/* CPCTRG = 1 (RC Compare resets the counter and restarts the clock) */
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/* WAVE = 0 (Capture mode enabled) */
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pTC->TC_CMR = 0x4004;
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/* TC Register C TC_RC (read/write) Compare Register 16-bits */
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/* */
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/* |----------------------------------|----------------------------------------| */
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/* | not used RC | */
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/* |----------------------------------|----------------------------------------| */
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/* 31 16 15 0 */
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/* */
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/* Timer Calculation: What count gives 1 msec time-out? */
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/* */
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/* TIMER_CLOCK5 = MCK / 1024 = 48054841 / 1024 = 46928 hz */
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/* */
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/* TIMER_CLOCK5 Period = 1 / 46928 = 21.309239686 microseconds */
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/* */
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/* A little algebra: .001 sec = count * 21.3092396896*10**-6 */
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/* count = .001 / 21.3092396896*10**-6 */
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/* count = 46.928 */
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/* */
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/* STK: Even Simpler, let the compiler do the work: */
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/* */
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/* TIMER_CLOCK5 = (MCK / 1024) / 1000 */
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/* = 48054841 / 1024 / 1000 = 46.928 */
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pTC->TC_RC = ((MCK / 1024 / 1000) + 1) * milliseconds;
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/* TC Interrupt Enable Register TC_IER (write-only) */
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/* */
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/* */
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/* |------------|-------|-------|-------|-------|--------|--------|--------|--------| */
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/* | ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS | */
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/* |------------|-------|-------|-------|-------|--------|--------|--------|--------| */
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/* 31 8 7 6 5 4 3 2 1 0 */
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/* */
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/* COVFS = 0 no effect <===== take default */
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/* 1 enable counter overflow interrupt */
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/* */
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/* LOVRS = 0 no effect <===== take default */
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/* 1 enable load overrun interrupt */
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/* */
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/* CPAS = 0 no effect <===== take default */
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/* 1 enable RA compare interrupt */
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/* */
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/* CPBS = 0 no effect <===== take default */
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/* 1 enable RB compare interrupt */
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/* */
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/* CPCS = 0 no effect */
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/* 1 enable RC compare interrupt <===== we select this one */
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/* */
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/* LDRAS = 0 no effect <===== take default */
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/* 1 enable RA load interrupt */
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/* */
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/* LDRBS = 0 no effect <===== take default */
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/* 1 enable RB load interrupt */
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/* */
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/* ETRGS = 0 no effect <===== take default */
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/* 1 enable External Trigger interrupt */
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/* */
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/* enable RC compare interrupt */
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pTC->TC_IER = 0x10;
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/* TC Interrupt Disable Register TC_IDR (write-only) */
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/* */
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/* */
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/* |------------|-------|-------|-------|-------|--------|--------|--------|--------| */
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/* | ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS | */
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/* |------------|-------|-------|-------|-------|--------|--------|--------|--------| */
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/* 31 8 7 6 5 4 3 2 1 0 */
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/* */
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/* COVFS = 0 no effect */
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/* 1 disable counter overflow interrupt <===== we select this one */
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/* */
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/* LOVRS = 0 no effect */
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/* 1 disable load overrun interrupt <===== we select this one */
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/* */
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/* CPAS = 0 no effect */
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/* 1 disable RA compare interrupt <===== we select this one */
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/* */
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/* CPBS = 0 no effect */
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/* 1 disable RB compare interrupt <===== we select this one */
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/* */
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/* CPCS = 0 no effect <===== take default */
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/* 1 disable RC compare interrupt */
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/* */
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/* LDRAS = 0 no effect */
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/* 1 disable RA load interrupt <===== we select this one */
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/* */
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/* LDRBS = 0 no effect */
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/* 1 disable RB load interrupt <===== we select this one */
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/* */
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/* ETRGS = 0 no effect */
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/* 1 disable External Trigger interrupt <===== we select this one */
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/* */
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/* disable all except RC compare interrupt */
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pTC->TC_IDR = 0xEF;
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}
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/* ***************************************************************************** */
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/* */
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/* Timer 0 Interrupt Service Routine */
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/* */
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/* Entered when Timer0 RC compare interrupt asserts */
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/* */
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/* Author: James P Lynch May 12, 2007 */
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/* Modified by Steve Karg */
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/* simplified and changed to a millisecond count-up timer */
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/* ***************************************************************************** */
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static void Timer0IrqHandler(
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void)
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{
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volatile AT91PS_TC pTC = AT91C_BASE_TC0; /* pointer to timer channel 0 register structure */
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volatile unsigned int dummy; /* temporary */
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/* read TC0 Status Register to clear interrupt */
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dummy = pTC->TC_SR;
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/* increment the tick count */
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Timer_Milliseconds++;
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if (SilenceTime < 60000)
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SilenceTime++;
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}
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int Timer_Silence(
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void)
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{
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return SilenceTime;
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}
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void Timer_Silence_Reset(
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void)
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{
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SilenceTime = 0;
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}
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/* ***************************************************************************** */
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/* */
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/* Timer 0 Initialization */
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/* */
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/* From James P Lynch main.c example code */
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/* Modified by Steve Karg */
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/* Moved timer startup code from main */
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/* modified the peripheral clock init */
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/* ***************************************************************************** */
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void TimerInit(
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void)
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{
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unsigned int pcsr;
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/* enable the Timer0 peripheral clock */
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volatile AT91PS_PMC pPMC = AT91C_BASE_PMC;
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pcsr = pPMC->PMC_PCSR;
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pPMC->PMC_PCER = pcsr | (1 << AT91C_ID_TC0);
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/* Set up the AIC registers for Timer 0 */
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volatile AT91PS_AIC pAIC = AT91C_BASE_AIC;
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/* Disable timer 0 interrupt */
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/* in AIC Interrupt Disable Command Register */
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pAIC->AIC_IDCR = (1 << AT91C_ID_TC0);
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/* Set the TC0 IRQ handler address in */
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/* AIC Source Vector Register[12] */
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pAIC->AIC_SVR[AT91C_ID_TC0] = (unsigned int) Timer0IrqHandler;
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/* Set the interrupt source type and priority */
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/* in AIC Source Mode Register[12] */
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pAIC->AIC_SMR[AT91C_ID_TC0] =
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(AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE | 0x4);
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/* Clear the TC0 interrupt */
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/* in AIC Interrupt Clear Command Register */
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pAIC->AIC_ICCR = (1 << AT91C_ID_TC0);
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/* Remove disable timer 0 interrupt */
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/* in AIC Interrupt Disable Command Reg */
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pAIC->AIC_IDCR = (0 << AT91C_ID_TC0);
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/* Enable the TC0 interrupt */
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/* in AIC Interrupt Enable Command Register */
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pAIC->AIC_IECR = (1 << AT91C_ID_TC0);
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/* Setup timer0 to generate a 1 msec periodic interrupt */
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Timer0_Setup(1);
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}
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