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This commit is contained in:
László Molnár 2006-07-24 11:06:06 +02:00
commit cf930d0dde
4 changed files with 2084 additions and 2115 deletions
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3613
src/stub/arm-linux.elf-entry.h
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File diff suppressed because it is too large Load Diff

6
src/stub/src/arch/arm/v4a/Makefile.extra
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@ -27,7 +27,11 @@ lzma_d_c%.S : tc_list = arm-lzma arm-linux.elf default
lzma_d_c%.S : tc_bfdname = elf32-littlearm lzma_d_c%.S : tc_bfdname = elf32-littlearm
tc.arm-lzma.gcc = $(tc.arm-linux.elf.gcc) tc.arm-lzma.gcc = $(tc.arm-linux.elf.gcc)
tc.arm-lzma.gcc += -march=armv4 -fPIC
# -fPIC not needed: no globals, no string constants, no &func.
# Omitting -fPIC enables general use of r10.
tc.arm-lzma.gcc += -march=armv4
tc.arm-lzma.gcc += -Os tc.arm-lzma.gcc += -Os
tc.arm-lzma.gcc += -ffunction-sections tc.arm-lzma.gcc += -ffunction-sections
tc.arm-lzma.gcc += -I$(UPX_LZMADIR) tc.arm-lzma.gcc += -I$(UPX_LZMADIR)

290
src/stub/src/arch/arm/v4a/lzma_d_cf.S
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@ -1,18 +1,18 @@
@ args = 12, pretend = 0, frame = 52 @ args = 12, pretend = 0, frame = 48
@ frame_needed = 0, uses_anonymous_args = 0 @ frame_needed = 0, uses_anonymous_args = 0
stmfd sp!, {r4, r5, r6, r7, r8, r9, fp, lr} stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
sub sp, sp, #52 sub sp, sp, #48
str r3, [sp, #0] str r3, [sp, #0]
ldrb r3, [r0, #0] @ zero_extendqisi2 ldrb r3, [r0, #0] @ zero_extendqisi2
ldrb r5, [r0, #2] @ zero_extendqisi2 ldrb r5, [r0, #2] @ zero_extendqisi2
ldrb lr, [r0, #1] @ zero_extendqisi2 ldrb lr, [r0, #1] @ zero_extendqisi2
ldr ip, [sp, #0] ldr ip, [sp, #0]
str r3, [sp, #24] str r3, [sp, #20]
ldr r3, [sp, #92] ldr r3, [sp, #92]
mov r4, #0 mov r4, #0
str r4, [ip, #0] str r4, [ip, #0]
str r4, [r3, #0] str r4, [r3, #0]
ldr ip, [sp, #24] ldr ip, [sp, #20]
ldrb r3, [r0, #1] @ zero_extendqisi2 ldrb r3, [r0, #1] @ zero_extendqisi2
add r3, ip, r3 add r3, ip, r3
mov ip, #768 mov ip, #768
@ -26,8 +26,8 @@
add r0, r0, #4 add r0, r0, #4
add ip, ip, #6 add ip, ip, #6
str r1, [sp, #4] str r1, [sp, #4]
str r3, [sp, #16] str r3, [sp, #12]
str lr, [sp, #20] str lr, [sp, #16]
str r0, [sp, #8] str r0, [sp, #8]
b f.L14 b f.L14
f.L15: f.L15:
@ -41,12 +41,12 @@ f.L14:
bne f.L15 bne f.L15
ldr r3, [sp, #4] ldr r3, [sp, #4]
mov r6, #0 mov r6, #0
add fp, r3, r2 add r9, r3, r2
mov lr, r3 mov lr, r3
mov r2, r6 mov r2, r6
f.L17: f.L17:
ldr r5, [sp, #4] ldr r5, [sp, #4]
rsb r3, r5, fp rsb r3, r5, r9
cmp r2, r3 cmp r2, r3
add lr, lr, #1 add lr, lr, #1
beq f.L18 beq f.L18
@ -55,52 +55,48 @@ f.L17:
cmp r2, #5 cmp r2, #5
orr r6, r3, r6, asl #8 orr r6, r3, r6, asl #8
bne f.L17 bne f.L17
mov r0, #0 mov fp, #0
mov ip, #1 mov ip, #1
str r0, [sp, #12] mov r7, fp
mov r7, r0
str r0, [sp, #28]
mvn r0, #0 mvn r0, #0
str ip, [sp, #48] str ip, [sp, #44]
str fp, [sp, #24]
str ip, [sp, #28]
str ip, [sp, #32] str ip, [sp, #32]
str ip, [sp, #36] str ip, [sp, #36]
str ip, [sp, #40]
b f.L172 b f.L172
f.L22: f.L22:
mvn r8, #-16777216 mvn r8, #-16777216
cmp r0, r8 cmp r0, r8
bhi f.L23 bhi f.L23
cmp lr, fp cmp lr, r9
beq f.L18 beq f.L18
ldrb r3, [lr], #1 @ zero_extendqisi2 ldrb r3, [lr], #1 @ zero_extendqisi2
mov r0, r0, asl #8 mov r0, r0, asl #8
orr r6, r3, r6, asl #8 orr r6, r3, r6, asl #8
f.L23: f.L23:
add r1, sp, #12 ldr r1, [sp, #12]
ldmia r1, {r1, r2} @ phole ldm ldr r2, [sp, #24]
ldr r3, [sp, #28] and sl, fp, r1
and r9, r1, r2 mov r1, r2, asl #4
mov r1, r3, asl #4 add r3, sl, r1
add r3, r9, r1
ldr r2, [sp, #8]
mov r5, r3, asl #1 mov r5, r3, asl #1
ldrh ip, [r2, r5] ldr r3, [sp, #8]
ldrh ip, [r3, r5]
mov r3, r0, lsr #11 mov r3, r0, lsr #11
mul r4, ip, r3 mul r4, ip, r3
cmp r6, r4 cmp r6, r4
bcs f.L26 bcs f.L26
ldr r0, [sp, #24] ldr r0, [sp, #20]
rsb r3, r0, #8 rsb r3, r0, #8
mov r3, r7, asr r3 mov r3, r7, asr r3
ldr r1, [sp, #12] ldr r1, [sp, #16]
ldr r0, [sp, #20] and r2, fp, r1
and r2, r1, r0 add r3, r3, r2, asl r0
ldr r1, [sp, #24]
add r3, r3, r2, asl r1
ldr r0, [sp, #8] ldr r0, [sp, #8]
mov r2, #1536 mov r2, #1536
mla r2, r3, r2, r0 mla r2, r3, r2, r0
ldr r1, [sp, #28] ldr r1, [sp, #24]
rsb r3, ip, #2048 rsb r3, ip, #2048
cmp r1, #6 cmp r1, #6
add r3, ip, r3, asr #5 add r3, ip, r3, asr #5
@ -110,24 +106,23 @@ f.L23:
movle r0, r4 movle r0, r4
movle r1, #1 movle r1, #1
ble f.L171 ble f.L171
ldr r2, [sp, #12] ldr r2, [sp, #44]
ldr r5, [sp, #48] ldr r5, [sp, #84]
ldr ip, [sp, #84] rsb r3, r2, fp
rsb r3, r5, r2 ldrb r7, [r5, r3] @ zero_extendqisi2
ldrb r7, [ip, r3] @ zero_extendqisi2
mov r0, r4 mov r0, r4
mov r1, #1 mov r1, #1
f.L31: f.L31:
mov r7, r7, asl #1 mov r7, r7, asl #1
and r5, r7, #256 and r5, r7, #256
mov r9, r1, asl #1 mov sl, r1, asl #1
add r3, r8, r5, asl #1 add r3, r8, r5, asl #1
add r3, r3, r9 add r3, r3, sl
cmp r0, #16777216 cmp r0, #16777216
add r4, r3, #512 add r4, r3, #512
add ip, r1, #1 add ip, r1, #1
bcs f.L32 bcs f.L32
cmp lr, fp cmp lr, r9
mov r0, r0, asl #8 mov r0, r0, asl #8
beq f.L18 beq f.L18
ldrb r3, [lr], #1 @ zero_extendqisi2 ldrb r3, [lr], #1 @ zero_extendqisi2
@ -145,7 +140,7 @@ f.L32:
cmp r5, #0 cmp r5, #0
mov r0, ip mov r0, ip
strh r2, [r4, #0] @ movhi strh r2, [r4, #0] @ movhi
mov r1, r9 mov r1, sl
beq f.L39 beq f.L39
mov r0, ip mov r0, ip
b f.L171 b f.L171
@ -163,7 +158,7 @@ f.L40:
cmp r0, #16777216 cmp r0, #16777216
add r1, r1, r3 add r1, r1, r3
bcs f.L41 bcs f.L41
cmp lr, fp cmp lr, r9
mov r0, r0, asl #8 mov r0, r0, asl #8
beq f.L18 beq f.L18
ldrb r3, [lr], #1 @ zero_extendqisi2 ldrb r3, [lr], #1 @ zero_extendqisi2
@ -188,24 +183,22 @@ f.L171:
add r3, r1, #1 add r3, r1, #1
ble f.L40 ble f.L40
f.L46: f.L46:
ldr ip, [sp, #24]
and r7, r1, #255 and r7, r1, #255
ldr r1, [sp, #28] cmp ip, #3
ldr r3, [sp, #12] ldr r1, [sp, #84]
ldr r2, [sp, #84] movle r2, #0
cmp r1, #3 strb r7, [r1, fp]
strb r7, [r2, r3] add fp, fp, #1
movle r5, #0 strle r2, [sp, #24]
add r3, r3, #1
str r3, [sp, #12]
strle r5, [sp, #28]
ble f.L172 ble f.L172
ldr ip, [sp, #28] ldr r3, [sp, #24]
cmp ip, #9 cmp r3, #9
ldrgt r1, [sp, #28] ldrgt r5, [sp, #24]
suble ip, ip, #3 suble r3, r3, #3
subgt r1, r1, #6 subgt r5, r5, #6
strle ip, [sp, #28] strle r3, [sp, #24]
strgt r1, [sp, #28] strgt r5, [sp, #24]
b f.L172 b f.L172
f.L26: f.L26:
sub r3, ip, ip, lsr #5 sub r3, ip, ip, lsr #5
@ -215,14 +208,14 @@ f.L26:
strh r3, [ip, r5] @ movhi strh r3, [ip, r5] @ movhi
rsb r6, r4, r6 rsb r6, r4, r6
bhi f.L51 bhi f.L51
cmp lr, fp cmp lr, r9
beq f.L18 beq f.L18
ldrb r3, [lr], #1 @ zero_extendqisi2 ldrb r3, [lr], #1 @ zero_extendqisi2
mov r2, r2, asl #8 mov r2, r2, asl #8
orr r6, r3, r6, asl #8 orr r6, r3, r6, asl #8
f.L51: f.L51:
ldr r0, [sp, #8] ldr r0, [sp, #8]
ldr r3, [sp, #28] ldr r3, [sp, #24]
add r7, r0, r3, asl #1 add r7, r0, r3, asl #1
add r0, r7, #384 add r0, r7, #384
ldrh ip, [r0, #0] ldrh ip, [r0, #0]
@ -230,23 +223,23 @@ f.L51:
mul r4, ip, r3 mul r4, ip, r3
cmp r6, r4 cmp r6, r4
bcs f.L54 bcs f.L54
ldr r2, [sp, #28] ldr r2, [sp, #24]
ldr r5, [sp, #8] ldr r5, [sp, #8]
cmp r2, #6 cmp r2, #6
rsb r3, ip, #2048 rsb r3, ip, #2048
add r1, r5, #1632 add r1, r5, #1632
movgt r2, #3 movgt r2, #3
ldr r5, [sp, #36] ldr r5, [sp, #32]
movle r2, #0 movle r2, #0
add r3, ip, r3, asr #5 add r3, ip, r3, asr #5
str r2, [sp, #28] str r2, [sp, #24]
ldr ip, [sp, #32] ldr ip, [sp, #28]
ldr r2, [sp, #48] ldr r2, [sp, #44]
str r5, [sp, #40] str r5, [sp, #36]
add r1, r1, #4 add r1, r1, #4
mov r5, r4 mov r5, r4
str ip, [sp, #36] str ip, [sp, #32]
str r2, [sp, #32] str r2, [sp, #28]
strh r3, [r0, #0] @ movhi strh r3, [r0, #0] @ movhi
b f.L59 b f.L59
f.L54: f.L54:
@ -256,7 +249,7 @@ f.L54:
strh r3, [r0, #0] @ movhi strh r3, [r0, #0] @ movhi
rsb r6, r4, r6 rsb r6, r4, r6
bhi f.L60 bhi f.L60
cmp lr, fp cmp lr, r9
beq f.L18 beq f.L18
ldrb r3, [lr], #1 @ zero_extendqisi2 ldrb r3, [lr], #1 @ zero_extendqisi2
mov r2, r2, asl #8 mov r2, r2, asl #8
@ -273,7 +266,7 @@ f.L60:
cmp r4, r8 cmp r4, r8
strh r3, [r5, #0] @ movhi strh r3, [r5, #0] @ movhi
bhi f.L67 bhi f.L67
cmp lr, fp cmp lr, r9
beq f.L18 beq f.L18
ldrb r3, [lr], #1 @ zero_extendqisi2 ldrb r3, [lr], #1 @ zero_extendqisi2
mov r4, r4, asl #8 mov r4, r4, asl #8
@ -281,7 +274,7 @@ f.L60:
f.L67: f.L67:
ldr r5, [sp, #8] ldr r5, [sp, #8]
add r3, r5, r1, asl #1 add r3, r5, r1, asl #1
add r3, r3, r9, asl #1 add r3, r3, sl, asl #1
add r1, r3, #480 add r1, r3, #480
ldrh ip, [r1, #0] ldrh ip, [r1, #0]
mov r3, r4, lsr #11 mov r3, r4, lsr #11
@ -293,23 +286,21 @@ f.L67:
bcs f.L169 bcs f.L169
rsb r3, ip, #2048 rsb r3, ip, #2048
add r3, ip, r3, asr #5 add r3, ip, r3, asr #5
ldr ip, [sp, #12] cmp fp, #0
cmp ip, #0
strh r3, [r1, #0] @ movhi strh r3, [r1, #0] @ movhi
beq f.L18 beq f.L18
ldr r0, [sp, #48] ldr ip, [sp, #44]
ldr r1, [sp, #84] ldr r1, [sp, #24]
rsb r3, r0, ip ldr r0, [sp, #84]
ldrb r7, [r1, r3] @ zero_extendqisi2 rsb r3, ip, fp
ldr r3, [sp, #28] ldrb r7, [r0, r3] @ zero_extendqisi2
cmp r3, #6 cmp r1, #6
movgt r3, #11 movgt r1, #11
movle r3, #9 movle r1, #9
str r3, [sp, #28] str r1, [sp, #24]
strb r7, [r0, fp]
mov r0, r2 mov r0, r2
strb r7, [r1, ip] add fp, fp, #1
add ip, ip, #1
str ip, [sp, #12]
b f.L172 b f.L172
f.L63: f.L63:
rsb r2, r4, r2 rsb r2, r4, r2
@ -318,7 +309,7 @@ f.L63:
strh r3, [r5, #0] @ movhi strh r3, [r5, #0] @ movhi
rsb r6, r4, r6 rsb r6, r4, r6
bhi f.L76 bhi f.L76
cmp lr, fp cmp lr, r9
beq f.L18 beq f.L18
ldrb r3, [lr], #1 @ zero_extendqisi2 ldrb r3, [lr], #1 @ zero_extendqisi2
mov r2, r2, asl #8 mov r2, r2, asl #8
@ -330,14 +321,14 @@ f.L76:
mul r4, ip, r3 mul r4, ip, r3
cmp r6, r4 cmp r6, r4
bcs f.L79 bcs f.L79
ldr r5, [sp, #48] ldr r5, [sp, #44]
rsb r3, ip, #2048 rsb r3, ip, #2048
ldr r2, [sp, #32] ldr r2, [sp, #28]
add r3, ip, r3, asr #5 add r3, ip, r3, asr #5
str r5, [sp, #32] str r5, [sp, #28]
mov r5, r4 mov r5, r4
f.L170: f.L170:
str r2, [sp, #48] str r2, [sp, #44]
f.L169: f.L169:
strh r3, [r1, #0] @ movhi strh r3, [r1, #0] @ movhi
b f.L75 b f.L75
@ -348,7 +339,7 @@ f.L79:
strh r3, [r1, #0] @ movhi strh r3, [r1, #0] @ movhi
rsb r6, r4, r6 rsb r6, r4, r6
bhi f.L81 bhi f.L81
cmp lr, fp cmp lr, r9
beq f.L18 beq f.L18
ldrb r3, [lr], #1 @ zero_extendqisi2 ldrb r3, [lr], #1 @ zero_extendqisi2
mov r2, r2, asl #8 mov r2, r2, asl #8
@ -361,41 +352,41 @@ f.L81:
cmp r6, r4 cmp r6, r4
bcs f.L84 bcs f.L84
rsb r3, ip, #2048 rsb r3, ip, #2048
ldr r2, [sp, #36] ldr r2, [sp, #32]
add r3, ip, r3, asr #5 add r3, ip, r3, asr #5
ldr r0, [sp, #48] ldr r0, [sp, #44]
ldr ip, [sp, #32] ldr ip, [sp, #28]
mov r5, r4 mov r5, r4
str ip, [sp, #36] str ip, [sp, #32]
str r0, [sp, #32] str r0, [sp, #28]
b f.L170 b f.L170
f.L84: f.L84:
sub r3, ip, ip, lsr #5 sub r3, ip, ip, lsr #5
strh r3, [r1, #0] @ movhi strh r3, [r1, #0] @ movhi
ldr ip, [sp, #48] ldr ip, [sp, #44]
add r1, sp, #36 add r1, sp, #32
ldmia r1, {r1, r3} @ phole ldm ldmia r1, {r1, r3} @ phole ldm
rsb r5, r4, r2 rsb r5, r4, r2
ldr r2, [sp, #32] ldr r2, [sp, #28]
str r1, [sp, #40] str r1, [sp, #36]
str r2, [sp, #36] str r2, [sp, #32]
str ip, [sp, #32] str ip, [sp, #28]
str r3, [sp, #48] str r3, [sp, #44]
rsb r6, r4, r6 rsb r6, r4, r6
f.L75: f.L75:
ldr r2, [sp, #28] ldr r2, [sp, #24]
ldr r0, [sp, #8] ldr r0, [sp, #8]
cmp r2, #6 cmp r2, #6
movgt r2, #11 movgt r2, #11
movle r2, #8 movle r2, #8
add r1, r0, #2656 add r1, r0, #2656
str r2, [sp, #28] str r2, [sp, #24]
add r1, r1, #8 add r1, r1, #8
f.L59: f.L59:
mvn r7, #-16777216 mvn r7, #-16777216
cmp r5, r7 cmp r5, r7
bhi f.L89 bhi f.L89
cmp lr, fp cmp lr, r9
beq f.L18 beq f.L18
ldrb r3, [lr], #1 @ zero_extendqisi2 ldrb r3, [lr], #1 @ zero_extendqisi2
mov r5, r5, asl #8 mov r5, r5, asl #8
@ -406,12 +397,12 @@ f.L89:
mul r4, ip, r3 mul r4, ip, r3
cmp r6, r4 cmp r6, r4
bcs f.L92 bcs f.L92
add r2, r1, r9, asl #4 add r2, r1, sl, asl #4
rsb r3, ip, #2048 rsb r3, ip, #2048
add r3, ip, r3, asr #5 add r3, ip, r3, asr #5
add r5, r2, #4 add r5, r2, #4
mov r0, r4 mov r0, r4
mov r9, #3 mov sl, #3
mov r8, #0 mov r8, #0
strh r3, [r1, #0] @ movhi strh r3, [r1, #0] @ movhi
b f.L94 b f.L94
@ -422,7 +413,7 @@ f.L92:
rsb r6, r4, r6 rsb r6, r4, r6
strh r3, [r1, #0] @ movhi strh r3, [r1, #0] @ movhi
bhi f.L95 bhi f.L95
cmp lr, fp cmp lr, r9
beq f.L18 beq f.L18
ldrb r3, [lr], #1 @ zero_extendqisi2 ldrb r3, [lr], #1 @ zero_extendqisi2
mov r2, r2, asl #8 mov r2, r2, asl #8
@ -433,12 +424,12 @@ f.L95:
mul r4, ip, r3 mul r4, ip, r3
cmp r6, r4 cmp r6, r4
bcs f.L98 bcs f.L98
add r2, r1, r9, asl #4 add r2, r1, sl, asl #4
rsb r3, ip, #2048 rsb r3, ip, #2048
add r3, ip, r3, asr #5 add r3, ip, r3, asr #5
add r5, r2, #260 add r5, r2, #260
mov r0, r4 mov r0, r4
mov r9, #3 mov sl, #3
mov r8, #8 mov r8, #8
strh r3, [r1, #2] @ movhi strh r3, [r1, #2] @ movhi
b f.L94 b f.L94
@ -448,10 +439,10 @@ f.L98:
rsb r6, r4, r6 rsb r6, r4, r6
rsb r0, r4, r2 rsb r0, r4, r2
add r5, r1, #516 add r5, r1, #516
mov r9, #8 mov sl, #8
mov r8, #16 mov r8, #16
f.L94: f.L94:
mov r7, r9 mov r7, sl
mov r1, #1 mov r1, #1
f.L100: f.L100:
add r3, r1, #1 add r3, r1, #1
@ -459,7 +450,7 @@ f.L100:
mov r4, r1, asl #1 mov r4, r1, asl #1
add r1, r1, r3 add r1, r1, r3
bcs f.L101 bcs f.L101
cmp lr, fp cmp lr, r9
mov r0, r0, asl #8 mov r0, r0, asl #8
beq f.L18 beq f.L18
ldrb r3, [lr], #1 @ zero_extendqisi2 ldrb r3, [lr], #1 @ zero_extendqisi2
@ -481,11 +472,11 @@ f.L101:
subs r7, r7, #1 subs r7, r7, #1
bne f.L100 bne f.L100
mov r2, #1 mov r2, #1
sub r3, r1, r2, asl r9 sub r3, r1, r2, asl sl
ldr r5, [sp, #28] ldr r5, [sp, #24]
add r3, r3, r8 add r3, r3, r8
cmp r5, #3 cmp r5, #3
str r3, [sp, #44] str r3, [sp, #40]
bgt f.L108 bgt f.L108
ldr ip, [sp, #8] ldr ip, [sp, #8]
cmp r3, #3 cmp r3, #3
@ -500,7 +491,7 @@ f.L110:
mov r4, r7, asl #1 mov r4, r7, asl #1
add r7, r7, r3 add r7, r7, r3
bcs f.L111 bcs f.L111
cmp lr, fp cmp lr, r9
mov r0, r0, asl #8 mov r0, r0, asl #8
beq f.L18 beq f.L18
ldrb r3, [lr], #1 @ zero_extendqisi2 ldrb r3, [lr], #1 @ zero_extendqisi2
@ -544,7 +535,7 @@ f.L123:
cmp r0, #16777216 cmp r0, #16777216
add r2, r2, #1 add r2, r2, #1
bcs f.L124 bcs f.L124
cmp lr, fp cmp lr, r9
mov r0, r0, asl #8 mov r0, r0, asl #8
beq f.L18 beq f.L18
ldrb r3, [lr], #1 @ zero_extendqisi2 ldrb r3, [lr], #1 @ zero_extendqisi2
@ -563,14 +554,14 @@ f.L124:
mov r5, ip, asl #4 mov r5, ip, asl #4
mov r7, #4 mov r7, #4
f.L122: f.L122:
mov r9, #1 mov sl, #1
mov r8, r9 mov r8, sl
f.L130: f.L130:
cmp r0, #16777216 cmp r0, #16777216
mov r1, r8, asl #1 mov r1, r8, asl #1
add ip, r8, #1 add ip, r8, #1
bcs f.L131 bcs f.L131
cmp lr, fp cmp lr, r9
mov r0, r0, asl #8 mov r0, r0, asl #8
beq f.L18 beq f.L18
ldrb r3, [lr], #1 @ zero_extendqisi2 ldrb r3, [lr], #1 @ zero_extendqisi2
@ -584,7 +575,7 @@ f.L131:
cmp r6, ip cmp r6, ip
add r2, r3, r2, asr #5 add r2, r3, r2, asr #5
sub r3, r3, r3, lsr #5 sub r3, r3, r3, lsr #5
orrcs r5, r5, r9 orrcs r5, r5, sl
movcc r8, r1 movcc r8, r1
movcc r0, ip movcc r0, ip
strcch r2, [r4, r1] @ movhi strcch r2, [r4, r1] @ movhi
@ -592,35 +583,32 @@ f.L131:
rsbcs r6, ip, r6 rsbcs r6, ip, r6
rsbcs r0, ip, r0 rsbcs r0, ip, r0
subs r7, r7, #1 subs r7, r7, #1
mov r9, r9, asl #1 mov sl, sl, asl #1
bne f.L130 bne f.L130
f.L137: f.L137:
adds r5, r5, #1 adds r5, r5, #1
str r5, [sp, #48] str r5, [sp, #44]
beq f.L139 beq f.L139
ldr r3, [sp, #28] ldr r3, [sp, #24]
add r3, r3, #7 add r3, r3, #7
str r3, [sp, #28] str r3, [sp, #24]
f.L108: f.L108:
ldr r5, [sp, #48] ldr r5, [sp, #44]
ldr ip, [sp, #12] cmp r5, fp
cmp r5, ip
bhi f.L18 bhi f.L18
rsb r3, r5, ip ldr ip, [sp, #40]
ldr r1, [sp, #44] ldr r1, [sp, #84]
ldr r5, [sp, #84] rsb r3, r5, fp
add r2, r1, #2 add r2, ip, #2
add r4, r5, r3 add r4, r1, r3
add ip, r5, ip add ip, r1, fp
f.L142: f.L142:
ldr r1, [sp, #12]
add r1, r1, #1
subs r2, r2, #1 subs r2, r2, #1
str r1, [sp, #12]
ldr r5, [sp, #88] ldr r5, [sp, #88]
moveq r3, #0 moveq r3, #0
movne r3, #1 movne r3, #1
cmp r1, r5 add fp, fp, #1
cmp fp, r5
movcs r3, #0 movcs r3, #0
andcc r3, r3, #1 andcc r3, r3, #1
ldrb r7, [r4], #1 @ zero_extendqisi2 ldrb r7, [r4], #1 @ zero_extendqisi2
@ -628,28 +616,26 @@ f.L142:
strb r7, [ip], #1 strb r7, [ip], #1
bne f.L142 bne f.L142
f.L172: f.L172:
ldr ip, [sp, #12] ldr ip, [sp, #88]
ldr r1, [sp, #88] cmp fp, ip
cmp ip, r1
bcc f.L22 bcc f.L22
f.L139: f.L139:
cmp r0, #16777216 cmp r0, #16777216
bcs f.L143 bcs f.L143
cmp lr, fp cmp lr, r9
beq f.L18 beq f.L18
add lr, lr, #1 add lr, lr, #1
f.L143: f.L143:
ldr r2, [sp, #4] ldr r0, [sp, #4]
ldr r5, [sp, #0] ldr r1, [sp, #0]
ldr r1, [sp, #12] ldr r2, [sp, #92]
ldr ip, [sp, #92] rsb r3, r0, lr
rsb r3, r2, lr
mov r0, #0 mov r0, #0
str r3, [r5, #0] str r3, [r1, #0]
str r1, [ip, #0] str fp, [r2, #0]
b f.L146 b f.L146
f.L18: f.L18:
mov r0, #1 mov r0, #1
f.L146: f.L146:
add sp, sp, #52 add sp, sp, #48
ldmfd sp!, {r4, r5, r6, r7, r8, r9, fp, pc} ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}

290
src/stub/src/arch/arm/v4a/lzma_d_cs.S
View File

@ -1,18 +1,18 @@
@ args = 12, pretend = 0, frame = 52 @ args = 12, pretend = 0, frame = 48
@ frame_needed = 0, uses_anonymous_args = 0 @ frame_needed = 0, uses_anonymous_args = 0
stmfd sp!, {r4, r5, r6, r7, r8, r9, fp, lr} stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
sub sp, sp, #52 sub sp, sp, #48
str r3, [sp, #0] str r3, [sp, #0]
ldrb r3, [r0, #0] @ zero_extendqisi2 ldrb r3, [r0, #0] @ zero_extendqisi2
ldrb r5, [r0, #2] @ zero_extendqisi2 ldrb r5, [r0, #2] @ zero_extendqisi2
ldrb lr, [r0, #1] @ zero_extendqisi2 ldrb lr, [r0, #1] @ zero_extendqisi2
ldr ip, [sp, #0] ldr ip, [sp, #0]
str r3, [sp, #24] str r3, [sp, #20]
ldr r3, [sp, #92] ldr r3, [sp, #92]
mov r4, #0 mov r4, #0
str r4, [ip, #0] str r4, [ip, #0]
str r4, [r3, #0] str r4, [r3, #0]
ldr ip, [sp, #24] ldr ip, [sp, #20]
ldrb r3, [r0, #1] @ zero_extendqisi2 ldrb r3, [r0, #1] @ zero_extendqisi2
add r3, ip, r3 add r3, ip, r3
mov ip, #768 mov ip, #768
@ -26,8 +26,8 @@
add r0, r0, #4 add r0, r0, #4
add ip, ip, #6 add ip, ip, #6
str r1, [sp, #4] str r1, [sp, #4]
str r3, [sp, #16] str r3, [sp, #12]
str lr, [sp, #20] str lr, [sp, #16]
str r0, [sp, #8] str r0, [sp, #8]
b s.L14 b s.L14
s.L15: s.L15:
@ -41,12 +41,12 @@ s.L14:
bne s.L15 bne s.L15
ldr r3, [sp, #4] ldr r3, [sp, #4]
mov r6, #0 mov r6, #0
add fp, r3, r2 add r9, r3, r2
mov lr, r3 mov lr, r3
mov r2, r6 mov r2, r6
s.L17: s.L17:
ldr r5, [sp, #4] ldr r5, [sp, #4]
rsb r3, r5, fp rsb r3, r5, r9
cmp r2, r3 cmp r2, r3
add lr, lr, #1 add lr, lr, #1
beq s.L18 beq s.L18
@ -55,52 +55,48 @@ s.L17:
cmp r2, #5 cmp r2, #5
orr r6, r3, r6, asl #8 orr r6, r3, r6, asl #8
bne s.L17 bne s.L17
mov r0, #0 mov fp, #0
mov ip, #1 mov ip, #1
str r0, [sp, #12] mov r7, fp
mov r7, r0
str r0, [sp, #28]
mvn r0, #0 mvn r0, #0
str ip, [sp, #48] str ip, [sp, #44]
str fp, [sp, #24]
str ip, [sp, #28]
str ip, [sp, #32] str ip, [sp, #32]
str ip, [sp, #36] str ip, [sp, #36]
str ip, [sp, #40]
b s.L172 b s.L172
s.L22: s.L22:
mvn r8, #-16777216 mvn r8, #-16777216
cmp r0, r8 cmp r0, r8
bhi s.L23 bhi s.L23
cmp lr, fp cmp lr, r9
beq s.L18 beq s.L18
ldrb r3, [lr], #1 @ zero_extendqisi2 ldrb r3, [lr], #1 @ zero_extendqisi2
mov r0, r0, asl #8 mov r0, r0, asl #8
orr r6, r3, r6, asl #8 orr r6, r3, r6, asl #8
s.L23: s.L23:
add r1, sp, #12 ldr r1, [sp, #12]
ldmia r1, {r1, r2} @ phole ldm ldr r2, [sp, #24]
ldr r3, [sp, #28] and sl, fp, r1
and r9, r1, r2 mov r1, r2, asl #4
mov r1, r3, asl #4 add r3, sl, r1
add r3, r9, r1
ldr r2, [sp, #8]
mov r5, r3, asl #1 mov r5, r3, asl #1
ldrh ip, [r2, r5] ldr r3, [sp, #8]
ldrh ip, [r3, r5]
mov r3, r0, lsr #11 mov r3, r0, lsr #11
mul r4, ip, r3 mul r4, ip, r3
cmp r6, r4 cmp r6, r4
bcs s.L26 bcs s.L26
ldr r0, [sp, #24] ldr r0, [sp, #20]
rsb r3, r0, #8 rsb r3, r0, #8
mov r3, r7, asr r3 mov r3, r7, asr r3
ldr r1, [sp, #12] ldr r1, [sp, #16]
ldr r0, [sp, #20] and r2, fp, r1
and r2, r1, r0 add r3, r3, r2, asl r0
ldr r1, [sp, #24]
add r3, r3, r2, asl r1
ldr r0, [sp, #8] ldr r0, [sp, #8]
mov r2, #1536 mov r2, #1536
mla r2, r3, r2, r0 mla r2, r3, r2, r0
ldr r1, [sp, #28] ldr r1, [sp, #24]
rsb r3, ip, #2048 rsb r3, ip, #2048
cmp r1, #6 cmp r1, #6
add r3, ip, r3, asr #5 add r3, ip, r3, asr #5
@ -110,24 +106,23 @@ s.L23:
movle r0, r4 movle r0, r4
movle r1, #1 movle r1, #1
ble s.L171 ble s.L171
ldr r2, [sp, #12] ldr r2, [sp, #44]
ldr r5, [sp, #48] ldr r5, [sp, #84]
ldr ip, [sp, #84] rsb r3, r2, fp
rsb r3, r5, r2 ldrb r7, [r5, r3] @ zero_extendqisi2
ldrb r7, [ip, r3] @ zero_extendqisi2
mov r0, r4 mov r0, r4
mov r1, #1 mov r1, #1
s.L31: s.L31:
mov r7, r7, asl #1 mov r7, r7, asl #1
and r5, r7, #256 and r5, r7, #256
mov r9, r1, asl #1 mov sl, r1, asl #1
add r3, r8, r5, asl #1 add r3, r8, r5, asl #1
add r3, r3, r9 add r3, r3, sl
cmp r0, #16777216 cmp r0, #16777216
add r4, r3, #512 add r4, r3, #512
add ip, r1, #1 add ip, r1, #1
bcs s.L32 bcs s.L32
cmp lr, fp cmp lr, r9
mov r0, r0, asl #8 mov r0, r0, asl #8
beq s.L18 beq s.L18
ldrb r3, [lr], #1 @ zero_extendqisi2 ldrb r3, [lr], #1 @ zero_extendqisi2
@ -145,7 +140,7 @@ s.L32:
cmp r5, #0 cmp r5, #0
mov r0, ip mov r0, ip
strh r2, [r4, #0] @ movhi strh r2, [r4, #0] @ movhi
mov r1, r9 mov r1, sl
beq s.L39 beq s.L39
mov r0, ip mov r0, ip
b s.L171 b s.L171
@ -163,7 +158,7 @@ s.L40:
cmp r0, #16777216 cmp r0, #16777216
add r1, r1, r3 add r1, r1, r3
bcs s.L41 bcs s.L41
cmp lr, fp cmp lr, r9
mov r0, r0, asl #8 mov r0, r0, asl #8
beq s.L18 beq s.L18
ldrb r3, [lr], #1 @ zero_extendqisi2 ldrb r3, [lr], #1 @ zero_extendqisi2
@ -188,24 +183,22 @@ s.L171:
add r3, r1, #1 add r3, r1, #1
ble s.L40 ble s.L40
s.L46: s.L46:
ldr ip, [sp, #24]
and r7, r1, #255 and r7, r1, #255
ldr r1, [sp, #28] cmp ip, #3
ldr r3, [sp, #12] ldr r1, [sp, #84]
ldr r2, [sp, #84] movle r2, #0
cmp r1, #3 strb r7, [r1, fp]
strb r7, [r2, r3] add fp, fp, #1
movle r5, #0 strle r2, [sp, #24]
add r3, r3, #1
str r3, [sp, #12]
strle r5, [sp, #28]
ble s.L172 ble s.L172
ldr ip, [sp, #28] ldr r3, [sp, #24]
cmp ip, #9 cmp r3, #9
ldrgt r1, [sp, #28] ldrgt r5, [sp, #24]
suble ip, ip, #3 suble r3, r3, #3
subgt r1, r1, #6 subgt r5, r5, #6
strle ip, [sp, #28] strle r3, [sp, #24]
strgt r1, [sp, #28] strgt r5, [sp, #24]
b s.L172 b s.L172
s.L26: s.L26:
sub r3, ip, ip, lsr #5 sub r3, ip, ip, lsr #5
@ -215,14 +208,14 @@ s.L26:
strh r3, [ip, r5] @ movhi strh r3, [ip, r5] @ movhi
rsb r6, r4, r6 rsb r6, r4, r6
bhi s.L51 bhi s.L51
cmp lr, fp cmp lr, r9
beq s.L18 beq s.L18
ldrb r3, [lr], #1 @ zero_extendqisi2 ldrb r3, [lr], #1 @ zero_extendqisi2
mov r2, r2, asl #8 mov r2, r2, asl #8
orr r6, r3, r6, asl #8 orr r6, r3, r6, asl #8
s.L51: s.L51:
ldr r0, [sp, #8] ldr r0, [sp, #8]
ldr r3, [sp, #28] ldr r3, [sp, #24]
add r7, r0, r3, asl #1 add r7, r0, r3, asl #1
add r0, r7, #384 add r0, r7, #384
ldrh ip, [r0, #0] ldrh ip, [r0, #0]
@ -230,23 +223,23 @@ s.L51:
mul r4, ip, r3 mul r4, ip, r3
cmp r6, r4 cmp r6, r4
bcs s.L54 bcs s.L54
ldr r2, [sp, #28] ldr r2, [sp, #24]
ldr r5, [sp, #8] ldr r5, [sp, #8]
cmp r2, #6 cmp r2, #6
rsb r3, ip, #2048 rsb r3, ip, #2048
add r1, r5, #1632 add r1, r5, #1632
movgt r2, #3 movgt r2, #3
ldr r5, [sp, #36] ldr r5, [sp, #32]
movle r2, #0 movle r2, #0
add r3, ip, r3, asr #5 add r3, ip, r3, asr #5
str r2, [sp, #28] str r2, [sp, #24]
ldr ip, [sp, #32] ldr ip, [sp, #28]
ldr r2, [sp, #48] ldr r2, [sp, #44]
str r5, [sp, #40] str r5, [sp, #36]
add r1, r1, #4 add r1, r1, #4
mov r5, r4 mov r5, r4
str ip, [sp, #36] str ip, [sp, #32]
str r2, [sp, #32] str r2, [sp, #28]
strh r3, [r0, #0] @ movhi strh r3, [r0, #0] @ movhi
b s.L59 b s.L59
s.L54: s.L54:
@ -256,7 +249,7 @@ s.L54:
strh r3, [r0, #0] @ movhi strh r3, [r0, #0] @ movhi
rsb r6, r4, r6 rsb r6, r4, r6
bhi s.L60 bhi s.L60
cmp lr, fp cmp lr, r9
beq s.L18 beq s.L18
ldrb r3, [lr], #1 @ zero_extendqisi2 ldrb r3, [lr], #1 @ zero_extendqisi2
mov r2, r2, asl #8 mov r2, r2, asl #8
@ -273,7 +266,7 @@ s.L60:
cmp r4, r8 cmp r4, r8
strh r3, [r5, #0] @ movhi strh r3, [r5, #0] @ movhi
bhi s.L67 bhi s.L67
cmp lr, fp cmp lr, r9
beq s.L18 beq s.L18
ldrb r3, [lr], #1 @ zero_extendqisi2 ldrb r3, [lr], #1 @ zero_extendqisi2
mov r4, r4, asl #8 mov r4, r4, asl #8
@ -281,7 +274,7 @@ s.L60:
s.L67: s.L67:
ldr r5, [sp, #8] ldr r5, [sp, #8]
add r3, r5, r1, asl #1 add r3, r5, r1, asl #1
add r3, r3, r9, asl #1 add r3, r3, sl, asl #1
add r1, r3, #480 add r1, r3, #480
ldrh ip, [r1, #0] ldrh ip, [r1, #0]
mov r3, r4, lsr #11 mov r3, r4, lsr #11
@ -293,23 +286,21 @@ s.L67:
bcs s.L169 bcs s.L169
rsb r3, ip, #2048 rsb r3, ip, #2048
add r3, ip, r3, asr #5 add r3, ip, r3, asr #5
ldr ip, [sp, #12] cmp fp, #0
cmp ip, #0
strh r3, [r1, #0] @ movhi strh r3, [r1, #0] @ movhi
beq s.L18 beq s.L18
ldr r0, [sp, #48] ldr ip, [sp, #44]
ldr r1, [sp, #84] ldr r1, [sp, #24]
rsb r3, r0, ip ldr r0, [sp, #84]
ldrb r7, [r1, r3] @ zero_extendqisi2 rsb r3, ip, fp
ldr r3, [sp, #28] ldrb r7, [r0, r3] @ zero_extendqisi2
cmp r3, #6 cmp r1, #6
movgt r3, #11 movgt r1, #11
movle r3, #9 movle r1, #9
str r3, [sp, #28] str r1, [sp, #24]
strb r7, [r0, fp]
mov r0, r2 mov r0, r2
strb r7, [r1, ip] add fp, fp, #1
add ip, ip, #1
str ip, [sp, #12]
b s.L172 b s.L172
s.L63: s.L63:
rsb r2, r4, r2 rsb r2, r4, r2
@ -318,7 +309,7 @@ s.L63:
strh r3, [r5, #0] @ movhi strh r3, [r5, #0] @ movhi
rsb r6, r4, r6 rsb r6, r4, r6
bhi s.L76 bhi s.L76
cmp lr, fp cmp lr, r9
beq s.L18 beq s.L18
ldrb r3, [lr], #1 @ zero_extendqisi2 ldrb r3, [lr], #1 @ zero_extendqisi2
mov r2, r2, asl #8 mov r2, r2, asl #8
@ -330,14 +321,14 @@ s.L76:
mul r4, ip, r3 mul r4, ip, r3
cmp r6, r4 cmp r6, r4
bcs s.L79 bcs s.L79
ldr r5, [sp, #48] ldr r5, [sp, #44]
rsb r3, ip, #2048 rsb r3, ip, #2048
ldr r2, [sp, #32] ldr r2, [sp, #28]
add r3, ip, r3, asr #5 add r3, ip, r3, asr #5
str r5, [sp, #32] str r5, [sp, #28]
mov r5, r4 mov r5, r4
s.L170: s.L170:
str r2, [sp, #48] str r2, [sp, #44]
s.L169: s.L169:
strh r3, [r1, #0] @ movhi strh r3, [r1, #0] @ movhi
b s.L75 b s.L75
@ -348,7 +339,7 @@ s.L79:
strh r3, [r1, #0] @ movhi strh r3, [r1, #0] @ movhi
rsb r6, r4, r6 rsb r6, r4, r6
bhi s.L81 bhi s.L81
cmp lr, fp cmp lr, r9
beq s.L18 beq s.L18
ldrb r3, [lr], #1 @ zero_extendqisi2 ldrb r3, [lr], #1 @ zero_extendqisi2
mov r2, r2, asl #8 mov r2, r2, asl #8
@ -361,41 +352,41 @@ s.L81:
cmp r6, r4 cmp r6, r4
bcs s.L84 bcs s.L84
rsb r3, ip, #2048 rsb r3, ip, #2048
ldr r2, [sp, #36] ldr r2, [sp, #32]
add r3, ip, r3, asr #5 add r3, ip, r3, asr #5
ldr r0, [sp, #48] ldr r0, [sp, #44]
ldr ip, [sp, #32] ldr ip, [sp, #28]
mov r5, r4 mov r5, r4
str ip, [sp, #36] str ip, [sp, #32]
str r0, [sp, #32] str r0, [sp, #28]
b s.L170 b s.L170
s.L84: s.L84:
sub r3, ip, ip, lsr #5 sub r3, ip, ip, lsr #5
strh r3, [r1, #0] @ movhi strh r3, [r1, #0] @ movhi
ldr ip, [sp, #48] ldr ip, [sp, #44]
add r1, sp, #36 add r1, sp, #32
ldmia r1, {r1, r3} @ phole ldm ldmia r1, {r1, r3} @ phole ldm
rsb r5, r4, r2 rsb r5, r4, r2
ldr r2, [sp, #32] ldr r2, [sp, #28]
str r1, [sp, #40] str r1, [sp, #36]
str r2, [sp, #36] str r2, [sp, #32]
str ip, [sp, #32] str ip, [sp, #28]
str r3, [sp, #48] str r3, [sp, #44]
rsb r6, r4, r6 rsb r6, r4, r6
s.L75: s.L75:
ldr r2, [sp, #28] ldr r2, [sp, #24]
ldr r0, [sp, #8] ldr r0, [sp, #8]
cmp r2, #6 cmp r2, #6
movgt r2, #11 movgt r2, #11
movle r2, #8 movle r2, #8
add r1, r0, #2656 add r1, r0, #2656
str r2, [sp, #28] str r2, [sp, #24]
add r1, r1, #8 add r1, r1, #8
s.L59: s.L59:
mvn r7, #-16777216 mvn r7, #-16777216
cmp r5, r7 cmp r5, r7
bhi s.L89 bhi s.L89
cmp lr, fp cmp lr, r9
beq s.L18 beq s.L18
ldrb r3, [lr], #1 @ zero_extendqisi2 ldrb r3, [lr], #1 @ zero_extendqisi2
mov r5, r5, asl #8 mov r5, r5, asl #8
@ -406,12 +397,12 @@ s.L89:
mul r4, ip, r3 mul r4, ip, r3
cmp r6, r4 cmp r6, r4
bcs s.L92 bcs s.L92
add r2, r1, r9, asl #4 add r2, r1, sl, asl #4
rsb r3, ip, #2048 rsb r3, ip, #2048
add r3, ip, r3, asr #5 add r3, ip, r3, asr #5
add r5, r2, #4 add r5, r2, #4
mov r0, r4 mov r0, r4
mov r9, #3 mov sl, #3
mov r8, #0 mov r8, #0
strh r3, [r1, #0] @ movhi strh r3, [r1, #0] @ movhi
b s.L94 b s.L94
@ -422,7 +413,7 @@ s.L92:
rsb r6, r4, r6 rsb r6, r4, r6
strh r3, [r1, #0] @ movhi strh r3, [r1, #0] @ movhi
bhi s.L95 bhi s.L95
cmp lr, fp cmp lr, r9
beq s.L18 beq s.L18
ldrb r3, [lr], #1 @ zero_extendqisi2 ldrb r3, [lr], #1 @ zero_extendqisi2
mov r2, r2, asl #8 mov r2, r2, asl #8
@ -433,12 +424,12 @@ s.L95:
mul r4, ip, r3 mul r4, ip, r3
cmp r6, r4 cmp r6, r4
bcs s.L98 bcs s.L98
add r2, r1, r9, asl #4 add r2, r1, sl, asl #4
rsb r3, ip, #2048 rsb r3, ip, #2048
add r3, ip, r3, asr #5 add r3, ip, r3, asr #5
add r5, r2, #260 add r5, r2, #260
mov r0, r4 mov r0, r4
mov r9, #3 mov sl, #3
mov r8, #8 mov r8, #8
strh r3, [r1, #2] @ movhi strh r3, [r1, #2] @ movhi
b s.L94 b s.L94
@ -448,10 +439,10 @@ s.L98:
rsb r6, r4, r6 rsb r6, r4, r6
rsb r0, r4, r2 rsb r0, r4, r2
add r5, r1, #516 add r5, r1, #516
mov r9, #8 mov sl, #8
mov r8, #16 mov r8, #16
s.L94: s.L94:
mov r7, r9 mov r7, sl
mov r1, #1 mov r1, #1
s.L100: s.L100:
add r3, r1, #1 add r3, r1, #1
@ -459,7 +450,7 @@ s.L100:
mov r4, r1, asl #1 mov r4, r1, asl #1
add r1, r1, r3 add r1, r1, r3
bcs s.L101 bcs s.L101
cmp lr, fp cmp lr, r9
mov r0, r0, asl #8 mov r0, r0, asl #8
beq s.L18 beq s.L18
ldrb r3, [lr], #1 @ zero_extendqisi2 ldrb r3, [lr], #1 @ zero_extendqisi2
@ -481,11 +472,11 @@ s.L101:
subs r7, r7, #1 subs r7, r7, #1
bne s.L100 bne s.L100
mov r2, #1 mov r2, #1
sub r3, r1, r2, asl r9 sub r3, r1, r2, asl sl
ldr r5, [sp, #28] ldr r5, [sp, #24]
add r3, r3, r8 add r3, r3, r8
cmp r5, #3 cmp r5, #3
str r3, [sp, #44] str r3, [sp, #40]
bgt s.L108 bgt s.L108
ldr ip, [sp, #8] ldr ip, [sp, #8]
cmp r3, #3 cmp r3, #3
@ -500,7 +491,7 @@ s.L110:
mov r4, r7, asl #1 mov r4, r7, asl #1
add r7, r7, r3 add r7, r7, r3
bcs s.L111 bcs s.L111
cmp lr, fp cmp lr, r9
mov r0, r0, asl #8 mov r0, r0, asl #8
beq s.L18 beq s.L18
ldrb r3, [lr], #1 @ zero_extendqisi2 ldrb r3, [lr], #1 @ zero_extendqisi2
@ -544,7 +535,7 @@ s.L123:
cmp r0, #16777216 cmp r0, #16777216
add r2, r2, #1 add r2, r2, #1
bcs s.L124 bcs s.L124
cmp lr, fp cmp lr, r9
mov r0, r0, asl #8 mov r0, r0, asl #8
beq s.L18 beq s.L18
ldrb r3, [lr], #1 @ zero_extendqisi2 ldrb r3, [lr], #1 @ zero_extendqisi2
@ -563,14 +554,14 @@ s.L124:
mov r5, ip, asl #4 mov r5, ip, asl #4
mov r7, #4 mov r7, #4
s.L122: s.L122:
mov r9, #1 mov sl, #1
mov r8, r9 mov r8, sl
s.L130: s.L130:
cmp r0, #16777216 cmp r0, #16777216
mov r1, r8, asl #1 mov r1, r8, asl #1
add ip, r8, #1 add ip, r8, #1
bcs s.L131 bcs s.L131
cmp lr, fp cmp lr, r9
mov r0, r0, asl #8 mov r0, r0, asl #8
beq s.L18 beq s.L18
ldrb r3, [lr], #1 @ zero_extendqisi2 ldrb r3, [lr], #1 @ zero_extendqisi2
@ -584,7 +575,7 @@ s.L131:
cmp r6, ip cmp r6, ip
add r2, r3, r2, asr #5 add r2, r3, r2, asr #5
sub r3, r3, r3, lsr #5 sub r3, r3, r3, lsr #5
orrcs r5, r5, r9 orrcs r5, r5, sl
movcc r8, r1 movcc r8, r1
movcc r0, ip movcc r0, ip
strcch r2, [r4, r1] @ movhi strcch r2, [r4, r1] @ movhi
@ -592,35 +583,32 @@ s.L131:
rsbcs r6, ip, r6 rsbcs r6, ip, r6
rsbcs r0, ip, r0 rsbcs r0, ip, r0
subs r7, r7, #1 subs r7, r7, #1
mov r9, r9, asl #1 mov sl, sl, asl #1
bne s.L130 bne s.L130
s.L137: s.L137:
adds r5, r5, #1 adds r5, r5, #1
str r5, [sp, #48] str r5, [sp, #44]
beq s.L139 beq s.L139
ldr r3, [sp, #28] ldr r3, [sp, #24]
add r3, r3, #7 add r3, r3, #7
str r3, [sp, #28] str r3, [sp, #24]
s.L108: s.L108:
ldr r5, [sp, #48] ldr r5, [sp, #44]
ldr ip, [sp, #12] cmp r5, fp
cmp r5, ip
bhi s.L18 bhi s.L18
rsb r3, r5, ip ldr ip, [sp, #40]
ldr r1, [sp, #44] ldr r1, [sp, #84]
ldr r5, [sp, #84] rsb r3, r5, fp
add r2, r1, #2 add r2, ip, #2
add r4, r5, r3 add r4, r1, r3
add ip, r5, ip add ip, r1, fp
s.L142: s.L142:
ldr r1, [sp, #12]
add r1, r1, #1
subs r2, r2, #1 subs r2, r2, #1
str r1, [sp, #12]
ldr r5, [sp, #88] ldr r5, [sp, #88]
moveq r3, #0 moveq r3, #0
movne r3, #1 movne r3, #1
cmp r1, r5 add fp, fp, #1
cmp fp, r5
movcs r3, #0 movcs r3, #0
andcc r3, r3, #1 andcc r3, r3, #1
ldrb r7, [r4], #1 @ zero_extendqisi2 ldrb r7, [r4], #1 @ zero_extendqisi2
@ -628,28 +616,26 @@ s.L142:
strb r7, [ip], #1 strb r7, [ip], #1
bne s.L142 bne s.L142
s.L172: s.L172:
ldr ip, [sp, #12] ldr ip, [sp, #88]
ldr r1, [sp, #88] cmp fp, ip
cmp ip, r1
bcc s.L22 bcc s.L22
s.L139: s.L139:
cmp r0, #16777216 cmp r0, #16777216
bcs s.L143 bcs s.L143
cmp lr, fp cmp lr, r9
beq s.L18 beq s.L18
add lr, lr, #1 add lr, lr, #1
s.L143: s.L143:
ldr r2, [sp, #4] ldr r0, [sp, #4]
ldr r5, [sp, #0] ldr r1, [sp, #0]
ldr r1, [sp, #12] ldr r2, [sp, #92]
ldr ip, [sp, #92] rsb r3, r0, lr
rsb r3, r2, lr
mov r0, #0 mov r0, #0
str r3, [r5, #0] str r3, [r1, #0]
str r1, [ip, #0] str fp, [r2, #0]
b s.L146 b s.L146
s.L18: s.L18:
mov r0, #1 mov r0, #1
s.L146: s.L146:
add sp, sp, #52 add sp, sp, #48
ldmfd sp!, {r4, r5, r6, r7, r8, r9, fp, pc} ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}